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CAT24FC02
2-kb I2C Serial EEPROM FEATURES
I 400 kHz (2.5 V) I2C bus compatible I 2.5 to 5.5 volt operation I Low power CMOS technology I 16-byte page write buffer I Industrial and extended temperature ranges I Self-timed write cycle with auto-clear I 1,000,000 program/erase cycles I 100 year data retention I 8-pin DIP, SOIC, TSSOP and MSOP packages
- "Green" package option available
I 256 x 8 memory organization I Hardware write protect
DESCRIPTION
The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24FC02 features a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP and MSOP packages.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
BLOCK DIAGRAM
SOIC Package (J, W, GW)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
TSSOP Package (U, Y, GY)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
SDA
START/STOP LOGIC
XDEC WP CONTROL LOGIC
E2PROM
MSOP Package (R, Z, GZ)
DATA IN STORAGE
A0 A1 A2 VSS
1 2 3 4
8 7 6 5
VCC WP SCL SDA
SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS
HIGH VOLTAGE/ TIMING CONTROL
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect 2.5 V to 5.5 V Power Supply Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1045, Rev. G
CAT24FC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V VCC with Respect to Ground ............. -2.0 V to +7.0 V Package Power Dissipation Capability (TA = 25C) .................................. 1.0 W RELIABILITY CHARACTERISTICS (3) Symbol NEND TDR VZAP ILTH(4) Parameter Endurance Data Retention ESD Susceptibility Latch-up
Lead Soldering Temperature (10 seconds) ...... 300C Output Short Circuit Current(2) ....................... 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Min 1,000,000 100 4000 100
Typ
Max
Units Cycles/Byte Years Volts mA
D.C. OPERATING CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Symbol ICC ICC ISB(5) ILI ILO VIL VIH VOL
Parameter Power Supply Current (Read) Power Supply Current (Write) Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0 V)
Test Conditions fSCL = 400 kHz fSCL = 400 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
Min
Typ
Max 1 3 1 1 1
Units mA mA A A A V V V
-1 VCC x 0.7 IOL = 3 mA
VCC x 0.3 VCC + 1.0 0.4
CAPACITANCE TA = 25C, f = 400 kHz, VCC = 5 V Symbol CI/O(3) CIN
(3)
Test Input/Output Capacitance (SDA) Input Capacitance (other pins)
Conditions VI/O = 0 V VIN = 0 V
Min
Typ
Max 8 6
Units pF pF
Note: (1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1.0 V to VCC + 1.0 V. (5) Maximum standby current (ISB) = 10A for the Extended Automotive temperature range.
Doc. No. 1072, Rev. G
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC02
A.C. CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits Symbol Parameter 2.5 V - 5.5 V Min FSCL TI(1) tAA tBUF
(1)
Max 400 100 900
Units kHz ns ns ns ns ns ns ns ns ns
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
0
1300 600 1300 600 600 0 100 300 300 600 100
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF
(1)
ns ns ns ns
tSU:STO tDH
Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1072, Rev. G
CAT24FC02
FUNCTIONAL DESCRIPTION
The CAT24FC02 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24FC02 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. A maximum of eight devices can be cascaded when using the device. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT24FC02 when this pin is tied to VCC, the entire array of memory is write protected. When left floating, memory is unprotected.
tR tLOW
PIN DESCRIPTIONS
SCL: Serial Clock The CAT24FC02 serial clock input pin is used to clock all Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHD:DAT tHIGH
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL START BIT STOP BIT
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc. No. 1072, Rev. G
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CAT24FC02
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24FC02 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
eight CAT24FC02 may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24FC02 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC02 then performs a Read or a Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24FC02 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. When the CAT24FC02 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC02 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24FC02 (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to Figure 4. Acknowledge Timing
SCL FROM MASTER 1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1072, Rev. G
CAT24FC02
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24FC02. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24FC02 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24FC02 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT24FC02 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten.
Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24FC02 in a single write cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT24FC02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24FC02 is still busy with the write operation, no ACK will be returned. If the CAT24FC02 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
WRITE PROTECTION
The CAT24FC02 is designed with a hardware protect pin that enables the user to protect the entire memory. Thehardware protection feature of the CAT24FC02 is designed into the part to provide added flexibility to the design engineers. The write protection feature of CAT24FC02 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire memory array is protected and becomes read only. The entire memory becomes write protected regardless of whether the write protect register has been written or not. When WP pin is tied to Vcc, the user cannot program the write protect register. If the WP pin is left floating or tied to Vss, the device can be written into.
Figure 6. Byte Write Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS
DATA
S T O P P
A C K
A C K
A C K
Figure 7. Page Write Timing
BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K SLAVE ADDRESS * A C K A C K A C K A C K BYTE ADDRESS (n) S T O P P
DATA n
DATA n+1
DATA n+P
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1072, Rev. G
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC02
Read Operations
The READ operation for the CAT24FC02 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24FC02 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. If N = 255, the counter will `wrap around' to address 0 and continue to clock out data. After the CAT24FC02 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24FC02 acknowledge the word
address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24FC02 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC02 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC02 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24FC02 is outputted sequentially with data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT24FC02 address bits so that the entire memory array can be read during one operation. If more than the 256 bytes are read out, the counter will "wrap around" and continue to clock out data bytes.
Figure 8. Immediate Address Read Timing
S T A R T S A C K DATA N O A C K S T O P P
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
SCL
8
9
SDA
8TH BIT DATA OUT NO ACK STOP
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
7
Doc No. 1072, Rev. G
CAT24FC02
Figure 9. Selective Read Timing
S T A R T S A C K A C K S T A R T S A C K DATA n N O A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
SLAVE ADDRESS
S T O P P
Figure 10. Sequential Read Timing
S T O P P A C K A C K A C K A C K N O A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
Doc. No. 1072, Rev. G
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC02
ORDERING INFORMATION
Prefix CAT Device # 24FC02 J Suffix I TE13 REV-E
Optional Company ID
Product Number
Temperature Range I = Industri E = Extended (-40C to +125C)
Die Revision: E, F
Package P: PDIP J: SOIC, JEDEC R: MSOP U: TSSOP L: PDIP (Lead-free, Halogen-free) W: SOIC, JEDEC (Lead-free, Halogen-free) Y: TSSOP (Lead-free, Halogen-free) Z: MSOP (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Tape & Reel
Notes: (1) The device used in the above example is a CAT24FC02JI-TE13 REV-E (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1072, Rev. G
REVISION HISTORY
Date 03/01/04 05/15/04 Revision Comments A B Initial Issue D.C. Operating Characteristics Write Cycle Limits Update Ordering Information Update Revision History Update Rev Number Update Write Cycle Limits Updated notes on page 2 Added Die Revision E in Ordering Information Updated Updated Updated Updated Updated Updated Updated Features Description Pin Function Reliability Characteristics Operating Characteristics A.C. Characteristics Ordering Information
06/07/04 7/27/2004 1/27/2005 03/23/2005
C D E F
08/02/2005
G
Update Pin Configuration Update Ordering Information
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Publication #: Revison: Issue date:
1072 G 08/02/05

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